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energy-efficient digital integrated circuits

Adam Teman

אדי תימן

Identity: verified

The Bar-Ilan CRIS profile identifies Adam Teman in the Faculty of Engineering; its record and the patent record align on his Bar-Ilan affiliation. [1]

Documented foundation

Research & experience

Bar-Ilan engineering faculty member and co-director of EnICS whose institutional record centers on energy-efficient integrated circuits and memories.[1]

low-power VLSI designSRAM and memory circuitsdigital implementation

CV and official profile

The institutional profile and publication record were inspected; no current downloadable CV was verified.[1]

Selected work

Representative records, not a complete publication list. Metadata confirms attribution; it does not independently replicate a result.

2020 · patent

Refresh Controller for First-In-First-Out Memories

The Bar-Ilan record identifies this as patent publication US2020168270 and names Adam Teman and Tzachi Noy as inventors.[2]

Patent evidence

14 catalogued patent records · 8 identified families · family unassigned for 6 records

Coverage: Partial inventor search

Partial inventor-name expansion across BGU, Bar-Ilan/BIRAD, Mellanox and RAAAM affiliations; 13 additional publication records inspected, including two related feedback gain-cell grants; publication count is not unique-invention count. Not exhaustive: no audited worldwide inventor-index export, current full CV or all RAAAM/EPFL name variants. Original US20170294221A1 remains in baseline; The bounded resolving pass directly inspected and added US9691445B2 and US10002660B2; both name Adam Teman. Their observed Google family IDs are 54358264 and 59999621, respectively. Retain both publications without treating their count as two distinct inventions. FIFO US10803920B2 adds a patent-table record for an invention already mentioned under baseline selected works. University list also self-reports provisional 62/775909; no public publication traced, so retained as an unresolved lead in notes.

Independent Reference Generation for Single RBL Memory Circuits

US20260105952A1 · Published 2026-04-16

Published patent document inspected

Publication assignee: Raaam Memory Technologies Ltd; Bar Ilan University

Named inventor Adam Teman; memory/digital-circuit subject and institutional inventor portfolio support the profile match. Affiliation/assignee is taken from this publication, not inferred from his present university. Both Raaam Memory Technologies Ltd and Bar Ilan University are observed; this is a 2026 application publication, not a grant.[187][224]

Physically-driven generation of many-ported storage arrays

US12498854B2 · Published 2025-12-16

Published patent document inspected

Publication assignee: Birad Research and Development Co Ltd

Named inventor Adam Teman; memory/digital-circuit subject and institutional inventor portfolio support the profile match. Affiliation/assignee is taken from this publication, not inferred from his present university.[179][224]

Skew-balancing algorithm for digital circuitry

US11556145B2 · Published 2023-01-17

Published patent document inspected

Publication assignee: Birad Research and Development Co Ltd

Named inventor Adam Teman; memory/digital-circuit subject and institutional inventor portfolio support the profile match. Affiliation/assignee is taken from this publication, not inferred from his present university.[175][224]

Fin-FET gain cells

US11127455B2 · Published 2021-09-21

Published patent document inspected

Publication assignee: Bar Ilan University

Named inventor Adam Teman; memory/digital-circuit subject and institutional inventor portfolio support the profile match. Affiliation/assignee is taken from this publication, not inferred from his present university.[171][224]

Show 9 moreShow fewer patent records

Complementary dual-modular redundancy memory cell

US10991421B2 · Published 2021-04-27

Published patent document inspected

Publication assignee: Bar Ilan University

Named inventor Adam Teman; memory/digital-circuit subject and institutional inventor portfolio support the profile match. Affiliation/assignee is taken from this publication, not inferred from his present university.[169][224]

Dynamic memory physical unclonable function

US10811073B2 · Published 2020-10-20

Published patent document inspected

Publication assignee: Birad Research and Development Co Ltd

Named inventor Adam Teman; memory/digital-circuit subject and institutional inventor portfolio support the profile match. Affiliation/assignee is taken from this publication, not inferred from his present university.[167][224]

Refresh controller for first-in first-out memories

US10803920B2 · Published 2020-10-13

Published patent document inspected

Publication assignee: Birad Research and Development Co Ltd

Named inventor Adam Teman; memory/digital-circuit subject and institutional inventor portfolio support the profile match. Affiliation/assignee is taken from this publication, not inferred from his present university. Its application publication US20200168270A1 was already mentioned under selected works; this adds the inspected grant to the patent table, not a newly discovered invention.[166][224]

High-density memory macro

US10497410B2 · Published 2019-12-03

Published patent document inspected

Publication assignee: Bar Ilan University; Mellanox Technologies Ltd

Named inventor Adam Teman; memory/digital-circuit subject and institutional inventor portfolio support the profile match. Affiliation/assignee is taken from this publication, not inferred from his present university. Both Bar Ilan University and Mellanox Technologies Ltd are observed as assignees.[163][224]

Transistor gain cell with feedback

US10002660B2 · Published 2018-06-19

Published patent document inspected

Publication assignee: Bar Ilan University

The exact inventor Adam TEMAN appears with Giterman, Meinerzhagen, Burg and Fish on the inspected feedback gain-cell publication, consistent with the retained baseline and previously read institutional inventor list. This additional publication is included despite related feedback gain-cell disclosures; it must not be counted as a distinct invention merely because it has a separate publication number. Google assigns source-specific family IDs; no invented merged family key is used.[161]

Transistor gain cell with feedback

US9691445B2 · Published 2017-06-27

Published patent document inspected

Publication assignee: Bar Ilan University

The exact inventor Adam TEMAN appears with Giterman, Meinerzhagen, Burg and Fish on the inspected feedback gain-cell publication, consistent with the retained baseline and previously read institutional inventor list. This additional publication is included despite related feedback gain-cell disclosures; it must not be counted as a distinct invention merely because it has a separate publication number. Google assigns source-specific family IDs; no invented merged family key is used.[208]

Original report snapshot

Original evidence: verified record

One attributable record was inspected; this is selective, not an exhaustive patent portfolio.[3]

Records are counted separately from identified families. Author-reported entries are labelled and may still need publication verification. Inventorship, publication-time applicant and current ownership are different facts. No legal-status, patentability or freedom-to-operate conclusion is made.

Scores prioritize research fit from 1–10; they are not probabilities.

Review: Reviewed with limitations

Proposed capability matches, not confirmed relationships. Scores are analyst judgments with low forecast confidence; researcher interests, capacity and feasibility need confirmation.

Internal connections

10 candidates

Connection 1

Leonid Yavits

Research fit

Original proposal

Proposal hypothesis: Teman's memory-circuit implementation and Yavits's processing-in-memory architecture connect directly at the energy cost of a genomic kernel.[1][104][105]

First test and score details

First test

Proposed first test: Replay one public sequence-classification workload through conventional and memory-centric models; compare memory accesses, latency and explicitly labelled energy estimates.

Score components

complementarity
3
feasible first test
3
topic overlap
4

Why this rank

Rank 1/10; fit 10/10 (4 topic overlap + 3 complementarity + 3 feasible first test). Preserved original co-membership proposal in o02. No strictly higher-scoring candidate displaces this original. Simulation is feasible without a tape-out; physical energy savings require later measured hardware. No automatic score boost for original membership. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work.

Connection 2

Alex Fish

Research fit

Original proposal

Proposal hypothesis: Teman and Fish both document low-power memory design; their useful division is digital implementation versus memory/sensor circuit tradeoffs on a common workload.[1][89][90]

First test and score details

First test

Proposed first test: Compare two SRAM/readout design models under identical access traces and voltage assumptions; report delay, retention/error assumptions and energy estimates.

Score components

complementarity
2
feasible first test
3
topic overlap
4

Why this rank

Rank 2/10; fit 9/10 (4 topic overlap + 2 complementarity + 3 feasible first test). Preserved original co-membership proposal in o02. Higher-scoring Leonid Yavits (10/10) precedes this original; its own rank reflects the following limitation: Very high topic overlap but substantial overlap in roles reduces complementarity relative to a circuit-architecture pairing. No automatic score boost for original membership. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work. Original initiative conditions remain: o02 Alex Fish: Alternative or later circuit lead: assess memory/circuit precision and energy tradeoffs if the chosen implementation needs this expertise; security is outside the initial test.

Connection 3

Moti Medina

Research fit

Proposal hypothesis: Teman's digital implementation and Medina's reliable hardware theory meet on the cost of preserving state under injected faults.[1][100]

First test and score details

First test

Proposed first test: Inject bounded memory/control faults into a small digital model and compare redundancy schemes on recovery and added state.

Score components

complementarity
3
feasible first test
3
topic overlap
3

Why this rank

Rank 3/10; fit 9/10 (3 topic overlap + 3 complementarity + 3 feasible first test). New pairing outside the frozen portfolio co-member graph. The fault model must be explicit; simulation is not radiation or silicon qualification. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work.

Show 7 moreShow fewer internal connections

Connection 4

Tomer Kalisky

Research fit

Original proposal

Proposal hypothesis: Teman can quantify energy and reduced-precision costs while Kalisky defines biological fidelity for a single-cell analysis pipeline.[1][70]

First test and score details

First test

Proposed first test: Quantize one public cell-state classifier and plot memory-access reduction against rare-cell recall and expression-derived state stability.

Score components

complementarity
3
feasible first test
2
topic overlap
2

Why this rank

Rank 4/10; fit 7/10 (2 topic overlap + 3 complementarity + 2 feasible first test). Preserved original co-membership proposal in o02. An added candidate, Moti Medina (9/10), ranks above this original because its stated pair-specific roles and first test score higher; this original is limited as follows: This cross-field link depends on a chosen computational kernel and biological labels; no wet-lab or chip availability is assumed. No automatic score boost for original membership. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work.

Connection 5

Yoli Shavit

Research fit

Original proposal

Proposal hypothesis: Teman's digital memory constraints provide controlled approximation settings for Shavit's proposed uncertainty-aware modelling of complex data.[1][127][128]

First test and score details

First test

Proposed first test: Quantize a small open multimodal model and compare calibration loss, prediction stability and memory footprint across held-out groups.

Score components

complementarity
3
feasible first test
2
topic overlap
2

Why this rank

Rank 5/10; fit 7/10 (2 topic overlap + 3 complementarity + 2 feasible first test). Preserved original co-membership proposal in o02. An added candidate, Moti Medina (9/10), ranks above this original because its stated pair-specific roles and first test score higher; this original is limited as follows: The original later-stage uncertainty role must follow a preregistered fidelity question; the announced biological programme is not demonstrated assay expertise. No automatic score boost for original membership. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work. Yoli Shavit biological/multimodal programme evidence is a 2025 announcement; current laboratory operation and biological experimental capability are not established. Original initiative conditions remain: o02 Yoli Shavit: Conditional later role: test uncertainty and generalization only after a specific cross-domain fidelity question is preregistered.

Connection 6

Ephraim Zehavi

Research fit

Proposal hypothesis: Teman's low-power memory implementation and Zehavi's coded wireless systems could trade local storage against retransmission energy.[1][19][20]

First test and score details

First test

Proposed first test: Model a sensor buffer under bursty link outages; compare buffer retention energy and retransmission cost for two policies.

Score components

complementarity
3
feasible first test
2
topic overlap
2

Why this rank

Rank 6/10; fit 7/10 (2 topic overlap + 3 complementarity + 2 feasible first test). New pairing outside the frozen portfolio co-member graph. A real radio/circuit energy model is needed before claiming battery-life savings. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work.

Connection 7

Yatir Sadia

Research fit

Proposal hypothesis: Sadia can define a plausible thermoelectric power envelope while Teman models digital memory behaviour under that intermittent supply.[1][31][32]

First test and score details

First test

Proposed first test: Replay synthetic power traces based on bounded thermoelectric assumptions through a memory/checkpoint model; measure lost work and energy overhead.

Score components

complementarity
3
feasible first test
2
topic overlap
2

Why this rank

Rank 7/10; fit 7/10 (2 topic overlap + 3 complementarity + 2 feasible first test). New pairing outside the frozen portfolio co-member graph. A complete energy harvester and realistic available power are not verified. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work.

Connection 8

Ran Gelles

Research fit

Proposal hypothesis: Teman can model intermittent memory state while Gelles defines which protocol state must survive for interactive computation to remain correct.[1][57][58]

First test and score details

First test

Proposed first test: Inject checkpoint losses into a small coded exchange and compare completed tasks and memory writes with full-state replication.

Score components

complementarity
3
feasible first test
2
topic overlap
2

Why this rank

Rank 8/10; fit 7/10 (2 topic overlap + 3 complementarity + 2 feasible first test). New pairing outside the frozen portfolio co-member graph. Memory faults and channel faults must be distinguished; no silicon fault tolerance is asserted. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work.

Connection 9

Benjamin M. Zaidel

Research fit

Proposal hypothesis: Teman's low-power digital memory constraints could expose the implementation cost of Zaidel's multiuser detection choices.[1][102]

First test and score details

First test

Proposed first test: Compare memory traffic and fixed-point error for two small MIMO detectors under identical channel assumptions.

Score components

complementarity
3
feasible first test
2
topic overlap
2

Why this rank

Rank 9/10; fit 7/10 (2 topic overlap + 3 complementarity + 2 feasible first test). New pairing outside the frozen portfolio co-member graph. Information-theoretic performance does not establish energy-efficient implementation. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work.

Connection 10

Anelia Somekh-Baruch

Research fit

Proposal hypothesis: Teman can expose memory read-error statistics while Somekh-Baruch asks whether a mismatched-decoding model captures their effect.[1][87]

First test and score details

First test

Proposed first test: Treat a small memory-read channel as a stated finite-alphabet model and compare two decoders under drift in error probabilities.

Score components

complementarity
3
feasible first test
2
topic overlap
1

Why this rank

Rank 10/10; fit 6/10 (1 topic overlap + 3 complementarity + 2 feasible first test). New pairing outside the frozen portfolio co-member graph. Classical channel models may omit correlated circuit faults, making this an exploratory abstraction. Equal scores use existing-first, then stable researcher ID.

Conditions

Analyst proposal hypothesis, not an established collaboration, commitment, evidence-confidence rating or assessment of researcher quality; confirm participation and access before work.

External connections

10 candidates

Connection 1

Jan M. Rabaey

University of California, Berkeley

Research fit

Original proposal

Rabaey's documented work in low-power integrated circuits, wireless systems and cyber-biological interaction complements Teman's memory and implementation expertise; this is a proposed match only.[1][4][488]

First test and score details

First test

Tape out or emulate one nonvolatile checkpointing block and measure energy, recovery latency and data integrity under harvested-power traces.

Score components

complementarity
3
feasible first test
2
topic overlap
4

Why this rank

Rank 1/10 after semantic revision; analyst score 9 = max(1, 4+3+2): topic overlap 4/4, complementarity 3/3, feasible first test 2/3. The experiment, numerical inputs or identity/scope needs confirmation before execution. Original remains first under these components; original status breaks equal-score ties only, without a prestige bonus.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified.

Connection 2

Srini Devadas

Massachusetts Institute of Technology

Research fit

Proposed capability match: Adam Teman's low-power VLSI design, SRAM and memory circuits can be paired with Srini Devadas's documented secure computer architecture, homomorphic-encryption accelerators for intermittent edge-ai chips for biological sensing. The specific contribution is hardware execution of privacy-preserving primitives; this transfer is an analyst hypothesis.[1][448]

First test and score details

First test

Replay a small encrypted-compute or proof-verification kernel under alternative memory and accelerator assumptions using an intermittently powered sensor-node memory/control workload. Compare runtime, memory traffic and explicitly stated leakage exposure with a fixed-duty sensor design with the same numerical output.

Score components

complementarity
3
feasible first test
2
topic overlap
3

Why this rank

Rank 2/10 after semantic revision; analyst score 8 = max(1, 3+3+2): topic overlap 3/4, complementarity 3/3, feasible first test 2/3. The experiment, numerical inputs or identity/scope needs confirmation before execution.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified.

Connection 3

Ali Javey

University of California, Berkeley

Research fit

Proposed capability match: Adam Teman's low-power VLSI design, SRAM and memory circuits can be paired with Ali Javey's documented low-power electronics, flexible electronics and sensors for intermittent edge-ai chips for biological sensing. The specific contribution is low-power device and sensor constraints; this transfer is an analyst hypothesis.[1][436]

First test and score details

First test

Screen two device operating points in a small power/noise model, requiring actual transfer curves before a device claim using an intermittently powered sensor-node memory/control workload. Compare predicted energy and sensitivity to device-parameter uncertainty with a fixed-duty sensor design with the same numerical output.

Score components

complementarity
3
feasible first test
2
topic overlap
3

Why this rank

Rank 3/10 after semantic revision; analyst score 8 = max(1, 3+3+2): topic overlap 3/4, complementarity 3/3, feasible first test 2/3. The experiment, numerical inputs or identity/scope needs confirmation before execution.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified.

Show 7 moreShow fewer external connections

Connection 4

Onur Mutlu

ETH Zurich

Research fit

Proposed capability match: Adam Teman's low-power VLSI design, SRAM and memory circuits can be paired with Onur Mutlu's documented memory systems, processing-in-memory for intermittent edge-ai chips for biological sensing. The specific contribution is memory placement and data-movement benchmarking; this transfer is an analyst hypothesis.[1][92][107][481]

First test and score details

First test

Replay identical traces under associative and conventional memory organizations using an intermittently powered sensor-node memory/control workload. Compare memory traffic, latency and an explicitly labelled energy proxy with a fixed-duty sensor design with the same numerical output.

Score components

complementarity
3
feasible first test
2
topic overlap
3

Why this rank

Rank 4/10 after semantic revision; analyst score 8 = max(1, 3+3+2): topic overlap 3/4, complementarity 3/3, feasible first test 2/3. The experiment, numerical inputs or identity/scope needs confirmation before execution.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified.

Connection 5

Borivoje Nikolic

University of California, Berkeley

Research fit

Proposed capability match: Adam Teman's low-power VLSI design, SRAM and memory circuits can be paired with Borivoje Nikolic's documented digital integrated circuits, VLSI implementation of communications for intermittent edge-ai chips for biological sensing. The specific contribution is digital implementation of a selected datapath; this transfer is an analyst hypothesis.[1][436]

First test and score details

First test

Synthesize two small datapath or memory-controller variants under identical constraints using an intermittently powered sensor-node memory/control workload. Compare area, timing slack and switching-activity power estimates with a fixed-duty sensor design with the same numerical output.

Score components

complementarity
2
feasible first test
2
topic overlap
4

Why this rank

Rank 5/10 after semantic revision; analyst score 8 = max(1, 4+2+2): topic overlap 4/4, complementarity 2/3, feasible first test 2/3. The experiment, numerical inputs or identity/scope needs confirmation before execution.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified.

Connection 6

Alberto Sangiovanni-Vincentelli

University of California, Berkeley

Research fit

Proposed capability match: Adam Teman's low-power VLSI design, SRAM and memory circuits can be paired with Alberto Sangiovanni-Vincentelli's documented embedded system design, control for intermittent edge-ai chips for biological sensing. The specific contribution is embedded component partitioning; this transfer is an analyst hypothesis.[1][436]

First test and score details

First test

Partition acquisition, computation and communication across two candidate embedded designs using an intermittently powered sensor-node memory/control workload. Compare interface overhead and end-to-end latency with a fixed-duty sensor design with the same numerical output.

Score components

complementarity
3
feasible first test
2
topic overlap
3

Why this rank

Rank 6/10 after semantic revision; analyst score 8 = max(1, 3+3+2): topic overlap 3/4, complementarity 3/3, feasible first test 2/3. The experiment, numerical inputs or identity/scope needs confirmation before execution.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified.

Connection 7

Sophia Shao

University of California, Berkeley

Research fit

Proposed capability match: Adam Teman's low-power VLSI design, SRAM and memory circuits can be paired with Sophia Shao's documented computer architecture, integrated circuits for intermittent edge-ai chips for biological sensing. The specific contribution is architecture and workload mapping; this transfer is an analyst hypothesis.[1][436]

First test and score details

First test

Map the same kernel to two accelerator organizations without changing numerical precision using an intermittently powered sensor-node memory/control workload. Compare data reuse, memory accesses and latency with a fixed-duty sensor design with the same numerical output.

Score components

complementarity
3
feasible first test
2
topic overlap
3

Why this rank

Rank 7/10 after semantic revision; analyst score 8 = max(1, 3+3+2): topic overlap 3/4, complementarity 3/3, feasible first test 2/3. The experiment, numerical inputs or identity/scope needs confirmation before execution.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified.

Connection 8

Clark Nguyen

University of California, Berkeley

Research fit

Proposed capability match: Adam Teman's low-power VLSI design, SRAM and memory circuits can be paired with Clark Nguyen's documented microelectromechanical sensors, timing and frequency control for intermittent edge-ai chips for biological sensing. The specific contribution is timing and RF sensor references; this transfer is an analyst hypothesis.[1][436]

First test and score details

First test

Inject clock drift and compare two timing-reference assumptions in a receiver model using an intermittently powered sensor-node memory/control workload. Compare synchronization error and energy spent reacquiring timing with a fixed-duty sensor design with the same numerical output.

Score components

complementarity
3
feasible first test
2
topic overlap
2

Why this rank

Rank 8/10 after semantic revision; analyst score 7 = max(1, 2+3+2): topic overlap 2/4, complementarity 3/3, feasible first test 2/3. The experiment, numerical inputs or identity/scope needs confirmation before execution.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified.

Connection 9

Pierluigi Nuzzo

University of California, Berkeley

Research fit

Proposed capability match: Adam Teman's low-power VLSI design, SRAM and memory circuits can be paired with Pierluigi Nuzzo's documented cyber-physical systems, design automation for intermittent edge-ai chips for biological sensing. The specific contribution is design automation and system requirements; this transfer is an analyst hypothesis.[1][436]

First test and score details

First test

Encode latency, energy and failure constraints in a small system model and inject single-component faults using an intermittently powered sensor-node memory/control workload. Compare constraint violations and recovery overhead with a fixed-duty sensor design with the same numerical output.

Score components

complementarity
3
feasible first test
2
topic overlap
2

Why this rank

Rank 9/10 after semantic revision; analyst score 7 = max(1, 2+3+2): topic overlap 2/4, complementarity 3/3, feasible first test 2/3. The experiment, numerical inputs or identity/scope needs confirmation before execution.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified.

Connection 10

Jun-Chau Chien

University of California, Berkeley

Research fit

Proposed capability match for Adam Teman with Jun-Chau Chien: Chien's biosensor interface could provide a concrete input specification for Teman's intermittent memory design; sensor and fluidic behavior are assumptions, so this is an interface study with indirect topic overlap.[1][436]

First test and score details

First test

Specify a synthetic two-channel electrochemical biosensor interface: digitized current samples, timestamps and blank-channel readings. Simulate ADC buffering and SRAM checkpoint/recovery under identical intermittent-power traces, comparing checkpoint policies at the same sample rate. Measure missing samples, reconstructed-current error and memory energy; do not infer fluid contamination from this digital model.

Score components

complementarity
2
feasible first test
2
topic overlap
2

Why this rank

Rank 10/10 after semantic revision; analyst score 6 = max(1, 2+2+2): topic overlap 2/4, complementarity 2/3, feasible first test 2/3. Chien's biosensor interface could provide a concrete input specification for Teman's intermittent memory design; sensor and fluidic behavior are assumptions, so this is an interface study with indirect topic overlap. The experiment, numerical inputs or identity/scope needs confirmation before execution.

Conditions

Proposed fit, not an assertion of a new or active relationship. Independent review pending; forecast confidence low. Partner interest, capacity, data access and any required experimental approvals/resources are unverified. Post-review scope: Chien's biosensor interface could provide a concrete input specification for Teman's intermittent memory design; sensor and fluidic behavior are assumptions, so this is an interface study with indirect topic overlap. This revised proposal awaits independent targeted re-review; simulated outcomes would establish model behavior only, not biological, clinical or deployed benefit.

Evidence & open questions

Inspect claim ratings and independent review

Adam Teman's documented expertise includes low-power digital circuits, memory design and digital implementation. [1][3]

High confidenceReview: reviewed

A current CV and exhaustive output review were not completed.

Review record
  • profiles_c: supports. The corrected claim removes unsupported hardware security. The opened Bar-Ilan profile supports low-power integrated-circuit and memory work, and the patent record confirms Teman's digital memory inventorship.

Hypothesis: Teman could lead resilient memory and digital design for intermittently powered biological edge sensors. [1][4]

Low confidenceReview: reviewed

The application, fabrication route and collaborator interest are unverified.

Review record
  • profiles_c: supports. Teman's low-power memory expertise and the newly opened Berkeley directory's sensor-network, low-power system, integrated-circuit and biomedical-interface fields ground the revised hypothesis.
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